List of Special Sessions

Paper # 901  Applying Cooperative Learning to a Graduate Power System
Analysis Course: It Works For Me!

Richard D. Christie     University of Washington

This paper give anecdotal experience about the application of
cooperative and active learning concepts in a graduate class in power
system analysis.  The use of these techniques resulted in a
significant improvement in student evaluations of the course (and the
instructor!) in comparison with two prior offerings


Paper # 902  Introducing Power Systems in an Undergraduate Machines
Lab

Thomas W. Gedra  Oklahoma State University

To illustrate the complexity of power system operation to juniors in
Energy Conversion I, a simple power system was constructed using
fractional-horsepower machines.  Students then operated the system
both with and without connection to the grid.  The lab setup and
student activities are described.  Other improvements to the OSU
undergraduate power curriculum are also discussed.


Paper # 903  Development and Application of a Power System Simulation
Environment

T. J. Overbye, R. P. Klump, and J. Weber  University of Illinois U-C

This paper describes a user-friendly power simulation package for
teaching power system operations and control.  This Microsoft Windows
based program simulates power system operation over a specified time
period (of typically several hours to a day).  Students dynamically
interact with the simulated system through various windows, including
a one-line display.  The use of data files and option windows allows
the program to simulate a wide variety of different power systems and
operating problems.


Paper # 904  Power System Engineering at the Sophomore Level

J. D. McCalley, V. Ajjarapu, G. B. Sheble', V. Vittal  Iowa State
University

This paper presents a course in power system analysis developed for
offering at the sophomore level as a part of the required
undergraduate electrical engineering curriculum at Iowa State
University.  We describe the criteria used in developing the course,
the topical coverage, and a set of computer modules, developed to
facilitate learning of particularly difficult concepts while
heightening student interest, that run in the MATLAB environment.


Paper # 905   A Virtual Electromechanical Machine Simulator

K. Olejniczak, T. W. Martin, W. G. Johnson   University of Arkansas

This paper presents an interactive virtual electromechanical machine
simulator designed to be an effective pedagogical tool for the
undergraduate and graduate program.  It has an user-friendly graphical
interface and consists of two distinct controller and electric machine
modules.  A virtual permanent- magnet brushless machine controlled by
a six-step inverter is presented in detail.


Paper # 906   A Multi-Institutional Cooperative Approach to Power
Engineering Education

M. L. Crow, S. D. Sudhoff  University of Missouri Rolla

A. Pahwa, S. Starrett   Kansas State University

K. Olejniczak    University of Arkansas

This paper will describe a multi-institutional project which has been
undertaken by the three participating universities to develop two
senior-level courses in flexible power system control.

Paper # 907   The Design of Integrated Magnetoresistive Devices

Art Pohm      Iowa State University

Magnetoresistive devices exhibiting the conventional anisotropic-
magnetoresistive-effect (AMR) or the new giant-magnetoresistance
effect (GMR) offer many possible solutions to both magnetic field
sensing and non-volatile storage.  The characteristics of these
devices will be described along with typical sensing strategies.


Paper # 908   Micromagnetics in Small Size AMR and GMR Devices

Jian-Gang Zhu    University of Minnesota

Magneto-electronic devices, such as magnetic random access memory
(MRAM), have generated significant research interest in recent years. 
Micromagnetic properties of these devices determine the performance
characteristics as well as the device stability and reliability.  In
this paper, microscopic magnetization processes in small AMR and GMR
devices are discussed with various examples of device designs using
advanced micromagnetic modeling analysis.


Paper # 909  A Non-Volatile 16k-bit MRAM Memory

Allan Hurst Jr.  Honeywell Solid-State Electronics Center

The design and experimental results from the first commercially viable
16k-bit non-volatile RAM using magnetoresistive memory elements will
be described.  The device allows unlimited read/write cycles and has a
read-cycle time of less than 250 nsec.  A description of memory
operation and various design details will be described.


Paper # 910  Spin-Valve Nonvolatile Memory Cell

Denny Tang    IBM Almaden Research Center

This paper will describe the design and experimental characteristics
of a nonvolatile memory cell using a GMR device.  As compared to
conventional AMR memory cells, sensing is significantly easier at
improve S/N because the memory-state related change in resistance is
independent of current passing through the resistor and produces a 30
mV output signal for a 6 micron long resistor.


Paper # 911  A Universal Low-Field Magnetic Field Sensor Using GMR
Resistors on a Semicustom Bi-CMOS Array.

Jay Brown    Nonvolatile Electronics Inc.

A universal mixed-mode BiCMOS array has been combined with GMR
resistors and plated field magnifiers to achieve a sensitive easily
reconfigurable low-field magnetic sensor.  The circuit may be
configured for either analog or digital outputs with full-scale ranges
of as low as 5 Gauss and may be used in applications of between 5 and
20 volts.


Paper #  912  Integrated GMR Isolation Technique

William Black  Iowa State University

Ted Hermann   Nonvolatile Electronics Inc.

A low-impedance isolated current loop has been integrated with a
magnetically- coupled CMOS compatible GMR resistor to achieve a linear
monolithic isolator with >1000 volts of standoff isolation.  Various
applications, including an isolated current replicator and an isolated
input A/D converter will be described.

Paper #913  A Field Programmable Analog Signal Processing Array

S.H.K. Embabi, X. Quan, N. Oki, A. Manjrekar, Edgar Sanchez-Sinencio
Texas A&M University

This paper presents a new approach towards Field Programmable Analog
Arrays (FPAA), which are dedicated to analog signal processing.  It is
based on simple current-mode sub-circuits which allows for operation
at high frequencies and low voltage, and can be implemented in a
digital CMOS process.  A novel solution to avoid using excessive
number of programming devices in the signal path is proposed.  We have
demonstrated through simulations that the proposed FPAA can be
programmed to operate over almost 3 decades (from 30 kHz to 10MHz)


Paper #914  Current Conveyors Field Programmable Analog Array

Christopher Premont    Cimirly Insa Lyon

An approach for designing field programmable analog array is
described. The analog array is based on current conveyors.  They are
used both as analog cells and interconnection elements.  Each
elementary cell is associated with tunable resistors and capacitors. 
The analog function is  implemented by using the elementary cells
programmed as current-mode amplifier or continuous-time filters.  The
first step of this approach is to be able to develop basic analog
functions such as low-frequency filtering and amplifying.  The current
conveyors and the tunable resistors have been fully simulated thanks
to Spice, and the layout design is in preparation. Future work will
consist of validating this new programmable topology.


Paper #915  Multi-Function Block for a Switched Current Field
Programmable Analog Array

Simon T. Chang, Barrie R. Hayes-Gill and Christopher J. Paul  
Nottingham University

This paper presents a Field Programmable Analog Array (FPAA) based on
switched-current (SI) signal processing technology.  A design
methodology for building complex switched current circuits using a
four phase clock is proposed.  A programmable building block, called
the "Multi-function Block," has been designed and can be used in a
FPAA to implement circuits based on this four phase technique.  The
block was fabricated using 0.7 (m CMOS and test results are presented.
Simulation software for circuits built using these MFBs was written in
C++. Example circuits, their implementation using MFBs and simulation
results generated by this software are also presented.


Paper #916  Reconfigurable Pipelined Data Converter Architecture

Edward K. F. Lee    Iowa State University

A reconfigurable pipelined data converter architecture suitable for
implementing Field-Programmable Mixed analog and digital Array (FPMA)
is described.  The proposed architecture can be reconfigured to a
number of different analog-to-digital converters and/or
digital-to-analog converters for a given number of conversion stages.
In addition, the resolution of the data converters can also be
programmed by scarifying the throughputs of the converters. 
Nevertheless, the throughputs are high due to the use of pipelined
structure.  Furthermore, using the reconfigurable digital hardware in
the FPMA, self-calibration schemes can also be implemented that allows
the proposed data converter architecture to have high accuracy.


Paper #917  The EPAC Architecture:  An Expert Cell Approach to Field
Programmable Analog Circuits

Hans W. Klein    IMP, Inc.

This paper describes the architectural configuration of the
Electrically Programmable Analog Circuit (EPAC), an expert cell
approach to meeting the market need for an analog counterpart to the
digital FPGA.  It provides an overview of the technology and describes
the internal operation of the first commercial EPAC devices.


Paper #918  Mixed-Mode Modeling and Simulation of a Field-Programmable
Analog Array Implementation of a Phased-Locked Loop

Edmund Pierzchala and Charles Wilson    Portland State University

The paper describes the results of behavioral modeling of a
phase-locked loop (PLL) implemented in a field-programmable analog
array (FPAA) of cellular structure.  The limitations of the particular
FPAA architecture and cell design (as used for the PLL implementation)
are explored using a mixed-mode (analog-digital) Saber simulator, and
its modeling language, MAST.


Paper #919  Behavioral Modelling and Simulation of a
Field-Programmable Analog Array (FPAA) Cell

Edmund Pierzchala, Ira Pollock, and Chee How Lim    Portland State
University

The paper presents behavioral modeling of the analog and digital
circuitry of a single cell of a field-programmable analog array (FPAA)
of cellular structure.  A model of the cell is developed using MAST
analog hardware description language (AHDL).  Mixed -mode capabilities
of MAST and the Saber simulator are used to examine the combined
performance of the analog and digital parts of the cell.  The impact
of the digital delays, D/A converter resolution, and other effects, as
well as the behavior of the analog part of the cell, are examined.

Paper #920     Transmit Pulse Shaping Filters and CORDIC Algorithm
Based Precompensation

Mark J. Vanderaar, Dale J. Mortensen, Ronald L. Bexten    NYMA, Inc.


Paper #921    Error Coding and Loss Cell Recovery in Asynchronous
Transfer Mode

W. W. Wu, M. U. Wu, J. Budinger, H. Kim    The Consultare Technology
Group, Inc.


Paper #922    Rad-Tolerand Flight VLSI From Commercial Foundries

Jody Gambles and Gary K. Maki     University of New Mexico


Paper #923    A Compact Cell Design for a Multiport Register File

Zhi Li, E. D. Smith, and S. C. Kwatra    The University of Toledo


Paper #924    VLSI Implementation of On Board Processing Subsystems
for Satellite Channels

M. M. Jamali, S. C. Kwatra    The University of Toledo


Paper #925  A High Speed array architecture for 2D wavelet transforms

Magdy Bayoumi         LSU

Paper #926    Adaptive Routing Algorithms for Wavelength-Routed
All-Optical Networks

Ahmed Mokhtar and Murat Azizoglu    University of Washington

This paper considers routing and wavelength assignment in
wavelength-routed, all-optical networks.  Algorithms are proposed for
adaptive routing of connection requests, which take into account the
current network state in an attempt to minimize the call blocking
probability. Analytical and simulation results are obtained for
comparative performance evaluating, and complexity issues are
addressed.


Paper #927  Towards Passive Wavelength-Routed Optical Networks

Dhritiman Banerjee and Biswanath Mukherjee    University of California

We explore an optical network architecture which employs dense WDM
technology and passive Waveguide Grating Routers (WGRs) to establish a
virtual topology based on lightpaths.  We examine the motivation and
the technical challenges involved in this approach, propose a network
design algorithm, and provide some illustrative performance results.


Paper #928  Wavelength Routers in WDM Local Area Networks

Michael S. Borella and Jason P. Jue    Depaul University

This paper presents a novel scheme for scheduling packet traffic on a
wavelength-division-multiplexed (WDM) local optical network which
employs a wavelength router.  An N-port latin router allows N2 x N2
connectivity via only N physical wavelengths.  We propose TDM schedule
for interconnecting MN nodes with a wavelength router. We show that
for non-zero transceiver tuning time, throughput on the order of N can
be achieved.


Paper #929  Channel-Sharing in Local Optical Networks

Srini Tridandapani    Iowa State University

We develop channel-sharing techniques in
wavelength-division-multiplexed (WDM), multi-channel, multi-hop
systems based on the technological limitation that the number of
channels, w, is less than the number of nodes, N, in the system.  We
show that having  w less than N channels is actually desirable from the
delay-performance point of view.  We obtain estimates for the optimal
number of channels which minimizes the average delay in the network.


Paper #930  Device/Performance Trade-Offs in All-Optical Networks

Richard A. Barry    MIT Lincoln Laboratory

This talk will focus on the benefits of using different classes of
optical and electro-optic devices for circuit switched all-optical WDM
networks. Two scenarios are considered:  passive LANs or MANs which
contain only passive optical devices, and configurable WANs which
contain many all-optical switching nodes connected in a nmesh
topology.


Paper #931  On WDM-ATM Network Architecture

Krishna M. Sivalingam    University of North Carolina

This paper proposes a hierarchical network architecture based on
all-optical Wavelength Division Multiplexed (WDM) networks extended
(for longer distances) through Asynchronous Transfer Mode (ATM)
networks.  The local subnetworks are designed as all-optical WDM
networks that require tunable components and a media-access protocol. 
The WDM networks will be interconnected using generalized multichannel
ATM switches that utilize multiple wavelengths on the input/output
links.

Paper #932  Optimal Energy Management for Solar Car Race

Graham S. Wright    University of Illinois at Urbana Champaign

This paper describes a solar car simulation and race strategy program
developed for the University of Illinois Sunrayce 95 solar car race
team. The strategy problem can be well posed as a global
time-minimization problem over the entire race.  This article
discusses the algorithms used some of our strategic insights and
expectations prior to the race, and how our battle plans fared in
contact with the enemy.


Paper #933  Continuous-Time Optimization of Gate Timing for
Synchronous Rectification

Jonathan Kimball, Philip T. Krein    University of Illinois at
Urbana-Champaign

Recent advances in electronics call for higher efficiency, lower
output voltage power converters.  On method proposed is to use
synchronous converters, which use two controlled switches (MOSFETs). 
A new algorithm is shown for adjusting the relative timing of the gate
signals to minimize input current, and therefore input power, for a
fixed output.  This is shown to be a member of a more general family
of analogy auto-tuning algorithms.  Implementation details and
experimental results follow.


Paper #934  Efficiency Analysis of Switched Capacitor Doubler

Pallab Midya    Motorola Chicago Corporate Research Laboratory

Switched capacitors doubler and triplers are used to step-up dc
voltage. They are readily integrable which makes them a good choice
for numerous applications.  Their power conversion efficiency is
limited due to switch drops, parasitic capacitances and resistances.
However their efficiency is also inherently limited by the circuit
topology.  This paper provides an upper bound for the power conversion
efficiency of a doubler assuming ideal components.  This analysis also
provides design guidelines, in terms of capacitor size and switching
frequency, for meeting efficiency goals. Finally an alternate circuit
topology is posed that would not have this efficiency bound.


Paper #935  An Improved Steady-State Method Applying Broyden's
Technique to the Shooting Method

Uma Ekambaram and Resve Saleh    University of Illinois

This paper presents an efficient steady-state analysis method
applicable to converter circuits.  The solution technique is based
upon the shooting method.  This method poses the steady state problem
as a boundary value problem by equating the states at the beginning
and end of a time period.  The equation that needs to be solved is a
nonlinear equation in the state transition function.  Previously this
equation was solved using Newton's method.  The new technique uses
Broyden's method to solve this equation.  This is faster, requires
significantly less matrix computation and is capable of handling
circuits which have internally and/or externally controlled switches
such as power converters, without necessarily taking switching time
variations into consideration.

Paper #936  Small Signal Analysis of PWM Voltage Mode and Current Mode
Control

Pallab Midya    Motorola Chicago Corporate Research Laboratory

Small signal analysis is commonly used in switched converter design. 
The PWM (pulse width modulation) block is usually approximated with a
single pole response.  The PWM block is a nonlinear block that
interacts with the control loop and is not accurately represented by
this model.  In this paper a time averaged analysis is presented that
computes the response of the PWM block in Voltage Mode and Current
Mode control.  This analysis models the PWM block with the control
loop and comes up with a gain and delay model.  This analysis also
yields qualitative data on the relative performance of voltage and
current mode controls.

RETURN TO MWSCAS 96 Home Page